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preliminary cy7s1061g, cy7s1061ge 16-mbit (1 m words 16 bit) static ram with deep-sleep feature and error-correcting code (ecc) cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-79707 rev. *g revised april 2, 2014 16-mbit (1 m words 16 bit) static ram with deep-sleep feature and error correcting code (ecc) features high speed ? t aa = 10 ns ultra-low power deep sleep (ds) current ? i ds = 22-a maximum low active and standby currents ? i cc = 90-ma typical ? i sb2 = 20-ma typical wide operating voltage range: 1.65 v to 2.2 v, 2.2 v to 3.6 v, and 4.5 v to 5.5 v embedded error-correcting code (ecc) for single-bit error correction 1.0-v data retention transistor-transistor logic (ttl) compatible inputs and outputs error indication (err) pin to indicate 1-bit error detection and correction available in pb-free 48-pin tsop i, 54-pin tsop ii, and 48-ball vfbga packages functional description the cy7s1061g is a high-performance cmos fast static ram organized as 1,048,576 words by 16 bits. this device features fast access times (10 ns) and a unique ultra-low power deep sleep mode. with sleep mode currents as low as 22 a, the cy7s1061g device combines the best features of fast and low-power sram in industry-standard package options. the device also features embedded ecc [1] . ecc logic can detect and correct single-bit error in the accessed location. the cy7s1061ge device includes an err pin that signals an error-detection and correction event during a read cycle to access devices with a single-chip enable input, assert the chip enable input (ce) low. to access dual chip enable devices, assert both chip enable inputs ? ce 1 as low and ce 2 as high. to perform data writes, assert the write enable (we ) input low, and provide the data and address on device data pins (i/o 0 through i/o 15 ) and address pins (a 0 through a 19 ) respectively. the byte high enable (bhe ) and byte low enable (ble ) inputs control byte writes, and write data on the corresponding i/o lines to the memory location specified. bhe controls i/o 8 through i/o 15 and ble controls i/o 0 through i/o 7 . to perform data reads, assert the output enable (oe ) input and provide the required address on the address lines. read data is accessible on the i/o lines (i/o 0 through i/o 15 ). you can perform byte accesses by asserting the required byte enable signal (bhe or ble ) to read either the upper byte or the lower byte of data from the specified address location. all i/os (i/o 0 through i/o 15 ) are placed in a high-impedance state when the device is deselected (ce high for single chip enable devices and ce 1 high and ce 2 low for dual chip enable devices), or the control signals (oe , ble , bhe ) are de-asserted. the device is placed in a low power deep sleep mode when the deep sleep pin (ds ) is low. in this state, the device is disabled for normal operation and is plac ed in a data retention mode. the device can be activated by de-asserting the deep sleep pin (ds high). the cy7s1061g is available in 48-pin tsop i, 54-pin tsop ii, and 48-ball vfbga packages. product portfolio product range v cc range (v) speed (ns) current consumption operating i cc (ma) standby, i sb2 ( m a) deep-sleep current (a) f = f max typ [2] max typ [2] max typ [1] max cy7s1061g18 industrial 1.65 v?2.2 v 15 70 80 20 30 8 22 cy7s1061g(e)30 2.2 v?3.6 v 10 90 110 cy7s1061g 4.5?5.5 v 10 90 110 notes 1. this device does not support automatic write-back on error detection. 2. typical values are included only for reference and are not guaranteed or tested. typical values are measured at v cc = 1.8 v (for a v cc range of 1.65 v?2.2 v), v cc = 3 v (for a v cc range of 2.2 v?3.6 v), and v cc = 5 v (for a v cc range of 4.5 v?5.5 v), t a = 25 c.
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 2 of 26 logic block diagram - cy7s1061g logic block diagram - cy7s1061ge
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 3 of 26 contents pin configurations ........................................................... 4 maximum ratings............................................................. 6 operating range............................................................... 6 dc electrical characteristics .......................................... 6 capacitance ...................................................................... 7 thermal resistance.......................................................... 7 ac test loads and waveforms....................................... 7 data retention characteristics ....................................... 8 data retention waveform................................................ 8 deep-sleep mode characteristics................................... 9 ac switching characteristics ....................................... 10 switching waveforms .................................................... 11 truth table ...................................................................... 15 err output ? cy7s1061ge........................................... 15 ordering information...................................................... 16 ordering code definitions ......................................... 16 package diagrams.......................................................... 17 acronyms ........................................................................ 20 document conventions ................................................. 20 units of measure ....................................................... 20 errata ............................................................................... 21 part numbers affected .............................................. 21 fast sram[45] qualification status........................ 21 fast sram[45] errata summa ry............................. 21 ac switching characteristics .................................... 22 document history page ................................................. 23 sales, solutions, and legal information ...................... 26 worldwide sales and design supp ort............. .......... 26 products .................................................................... 26 psoc? solutions ...................................................... 26 cypress developer community................................. 26 technical support .................. ................................... 26
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 4 of 26 pin configurations figure 1. 48-ball vfbga (6 8 1.0 mm) pinout (top view) [3] figure 2. 54-pin tsop ii (22.4 11.84 1.0 mm) pinout [3] we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe a 7 i/o 0 bhe ds a 17 a 2 a 1 ble i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 a 19 a 18 nc 3 26 5 4 1 d e b a c f g h a 16 nc v cc v cc v ss 1 2 3 4 5 6 7 8 9 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 i/o 11 18 17 20 19 23 28 25 24 22 21 27 26 v ss i/o 10 i/o 12 v cc i/o 13 i/o 14 v ss a 16 a 17 a 11 a 12 a 13 a 14 i/o 0 a 15 i/o 7 i/o 9 v cc i/o 8 i/o 15 a 19 a 4 a 3 a 2 a 1 ce 1 v cc we ce 2 ble ds v ss oe a 8 a 7 a 6 a 5 a 0 nc a 9 bhe a 10 10 a 18 46 45 47 50 49 48 51 54 53 52 i/o 2 i/o 1 i/o 3 v ss v cc v ss i/o 6 i/o 5 v cc i/o 4 note 3. nc pins are not connected internally to the die.
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 5 of 26 figure 3. 48-pin tsop i (12 18.4 1 mm) pinout (top view) [4] figure 4. 48-pin tsop i (12 18.4 1 mm) pinout, err output at pin 6 (top view) pin configurations (continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a 4 a 3 a 2 a 1 a 0 nc ce i/o 0 i/o 1 i/o 2 i/o 3 v dd gnd i/o 4 i/o 5 i/o 6 i/o 7 we ds a 19 a 18 a 17 a 16 a 15 a 5 a 6 a 7 a 8 oe bhe ble i/o 15 i/o 14 i/o 13 i/o 12 gnd v dd i/o 11 i/o 10 i/o 9 i/o 8 nc a 9 a 10 a 11 a 12 a 13 a 14 note 4. nc pins are not connected internally to the die.
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 6 of 26 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 c to +150 c ambient temperature with power applied .... .............. .............. .......... ?55 c to +125 c supply voltage on v cc relative to gnd [5] .........................................?0.5 v to +6.0 v dc voltage applied to outputs in high z state [5] ................................. ?0.5 v to v cc + 0.5 v dc input voltage [5] .............................. ?0.5 v to v cc + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (mil-std-883, method 3015) ................................. > 2001 v latch-up current .................................................... > 140 ma operating range range ambient temperature v cc industrial ?40 c to +85 c 1.65 v to 2.2 v, 2.2 v to 3.6 v, 4.5 v to 5.5 v dc electrical characteristics over the operating range of ?40 c to +85 c parameter description test conditions 10 ns / 15 ns unit min typ [8] max v oh output high voltage 1.65 v to 2.2 v v cc = min, i oh = ?0.1 ma 1.4 ? ? v 2.2 v to 2.7 v v cc = min, i oh = ?1.0 ma 2.0 ? ? 2.7 v to 3.6 v v cc = min, i oh = ?4.0 ma 2.2 ? ? 4.5 v to 5.5 v v cc = min, i oh = ?4.0 ma 2.4 ? ? v ol output low voltage 1.65 v to 2.2 v v cc = min, i ol = 0.1 ma ? ? 0.2 v 2.2 v to 2.7 v v cc = min, i ol = 2 ma ? ? 0.4 2.7 v to 3.6 v v cc = min, i ol = 8 ma ? ? 0.4 4.5 v to 5.5 v v cc = min, i ol = 8 ma ? ? 0.4 v ih [5, 6] input high voltage 1.65 v to 2.2 v ? 1.4 ? v cc + 0.2 v 2.2 v to 2.7 v ? 2.0 ? v cc + 0.3 2.7 v to 3.6 v ? 2.0 ? v cc + 0.3 4.5 v to 5.5 v ? 2.2 ? v cc + 0.5 v il [5, 6] input low voltage 1.65 v to 2.2 v ? ?0.2 ? 0.4 v 2.2 v to 2.7 v ? ?0.3 ? 0.6 2.7 v to 3.6 v ? ?0.3 ? 0.8 4.5 v to 5.5 v ? ?0.5 ? 0.8 i ix input leakage current gnd < v in < v cc ?1.0 ? +1.0 a i oz output leakage current gnd < v out < v cc , output disabled ?1.0 ? +1.0 a i cc v cc operating supply current v cc = max, i out = 0 ma, cmos levels f = 100 mhz ? 90.0 110.0 ma f = 66.7 mhz ? 70.0 80.0 i sb1 standby current ? ttl inputs max v cc , ce [7] > v ih , v in > v ih or v in < v il , f = f max ??40.0ma i sb2 standby current ? cmos inputs max v cc , ce [7] > v cc ? 0.2 v, ds > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0 ?20.030.0ma i ds deep-sleep current max v cc , ce [7] > v cc ? 0.2 v, ds < 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0 ? 8.0 22.0 a notes 5. v il (min) = ?2.0 v and v ih (max) = v cc + 2 v for pulse durations of less than 2 ns. 6. for ds pin, v ih (min) is v cc ? 0.2 v and v il (max) is 0.2 v. 7. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 8. typical values are included only for reference and are not guaranteed or tested. typical values are measured at v cc = 1.8 v (for a v cc range of 1.65 v?2.2 v), v cc = 3 v (for a v cc range of 2.2 v?3.6 v), and v cc = 5 v (for a v cc range of 4.5 v?5.5 v), t a = 25 c.
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 7 of 26 capacitance parameter [9] description test conditions all packages unit c in input capacitance t a = 25 c, f = 1 mhz, v cc(typ) 10 pf c out i/o capacitance 10 pf thermal resistance parameter [9] description test conditions 48-ball vfbga 54-pin tsop ii 48-pin tsop i unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four layer printed circuit board 31.50 93.63 57.99 c/w jc thermal resistance (junction to case) 15.75 21.58 13.42 c/w ac test loads and waveforms figure 5. ac test loads and waveforms [10] 90% 10% v high gnd 90% 10% all input pulses v cc output 5 pf* * including jig and scope (b) r1 r2 rise time: fall time: > 1 v/ns (c) output 50 z 0 = 50 v th 30 pf* * capacitive load consists of all components of the test environment high-z characteristics: (a) > 1 v/ns parameters 1.8 v 3.0 v 5.0 v unit r1 1667 317 317 r2 1538 351 351 v th v cc /2 1.5 1.5 v v high 1.8 3.0 3.0 v notes 9. tested initially and after any design or process changes that may affect these parameters. 10. full-device ac operation assumes a 100- s ramp time from 0 to v cc (min) and100- s wait time after v cc stabilizes to its operational value.
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 8 of 26 data retention characteristics over the operating range of ?40 c to +85 c parameter description conditions min max unit v dr v cc for data retention 1.0 ? v i ccdr data retention current v cc = v dr , ce > v cc ? 0.2 v, ds > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ?30.0ma t cdr [11] chip deselect to data retention time 0?ns t r [11] operation recovery time 2.2 v < v cc < 5.5 v 10.0 ? ns v cc < 2.2 v 15.0 ? ns data retention waveform figure 6. data retention waveform [12, 13] t cdr t r v dr = 1.0 v data retention mode v cc(min) v cc(min) v cc ce notes 11. tested initially and after any design or proce ss changes that may affect these parameters. 12. full device operation requires linear v cc ramp from v dr to v cc (min) > 100 s or stable at v cc (min) > 100 s. 13. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high.
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 9 of 26 deep-sleep mode characteristics over the operating range of ?40 c to +85 c parameter description conditions min max unit i ds deep sleep mode current v cc = v cc (max), ce [14] > v cc ? 0.2 v, ds < 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v ?22a t ceds [14] time between de-assertion of ce [14] and assertion of ds 100 ? ns t ds [14] ds assertion to deep-sleep mode transition time ?1ms t dsce [14] time between de-assertion of ds and assertion of ce [14] 1?ms figure 7. active, standby, and deep-sleep operation modes [15] ds ce mode active ? mode standby ? mode deep ? sleep ? mode t ceds t ds t dsce notes 14. address, data, and control lines should not toggle within t ds . they should be fixed to one of the logic levels- v ih or v il 15. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high.
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 10 of 26 ac switching characteristics over the operating range of ?40 c to +85 c parameter [16] description 10 ns 15 ns unit min max min max read cycle t power v cc (stable) to the first access [17] 100.0 - 100.0 - s t rc read cycle time 10.0 ? 15.0 ? ns t aa address to data valid / err valid ? 10.0 ? 15.0 ns t oha data / err hold from address change 3.0 ? 3.0 ? ns t ace ce low to data valid / err valid ? 10.0 ? 15.0 ns t doe oe low to data valid / err valid ? 5.0 ? 8.0 ns t lzoe oe low to low-z [18 , 19] 0?1.0? ns t hzoe oe high to high-z [18 , 19] ? 5.0 ? 8.0 ns t lzce ce low to low-z [18, 19, 20] 3.0?3.0? ns t hzce ce high to high-z [18, 19, 20] ? 5.0 ? 8.0 ns t pu ce low to power-up [ 21] 0?0? ns t pd ce high to power-down [ 21] ? 10.0 ? 15.0 ns t dbe byte enable to data valid ? 5.0 ? 8.0 ns t lzbe byte enable to low-z [18, 19] 0?1.0? ns t hzbe byte disable to high-z [18, 19] ? 5.0 ? 8.0 ns write cycle [22, 23] t wc write cycle time 10.0 ? 15.0 ? ns t sce ce low to write end [20] 7.0 ? 12.0 ? ns t aw address setup to write end 7.0 ? 12.0 ? ns t ha address hold from write end 0? 0 ? ns t sa address setup to write start 0 ? 0 ? ns t pwe we pulse width 7.0 ? 12.0 ? ns t sd data setup to write end 5.0 ? 8.0 ? ns t hd data hold from write end 0 ? 0 ? ns t lzwe we high to low-z [18, 19] 3.0?3.0? ns t hzwe we low to high-z [18, 19] ? 5.0 ? 8.0 ns t bw byte enable to end of write 7.0 ? 12.0 ? ns notes 16. test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 v (for v cc > 3 v) and v cc /2 (for v cc < 3 v), and input pulse levels of 0 to 3 v (for v cc > 3 v), and 0 to v cc (for v cc < 3v). test conditions for the read cycle us e the output lo ading shown in part (a) of figure 5 on page 7 , unless specified otherwise 17. t power gives the minimum amount of time that the power supply is at stable v cc until the first memory access is performed 18. t hzoe , t hzce , t hzwe , t hzbe , t lzoe , t lzce , t lzwe , and t lzbe are specified with a load capacitance of 5 pf, as shown in part (b) of figure 5 on page 7 . transition is measured 200 mv from steady state voltage. 19. at any temperature and voltage condition, t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any device. 20. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 21. these parameters are guaranteed by design and are not tested. 22. the internal write time of the memory is defined by the overlap of we = v il , ce = v il , and bhe or ble = v il . these signals must be low to initiate a write, and the high transition of any of these signals can terminate the operation. the input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 23. the minimum write pulse width for write cycle no. 2 (we controlled, oe low) should be the sum of t hzwe and t sd .
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 11 of 26 switching waveforms figure 8. read cycle no. 1 of cy7s 1061g(address transition controlled) [24, 25] figure 9. read cycle no. 2 of cy7s 1061ge (address transition controlled) [24, 25] address data i/o previous data out valid data out valid t rc t oha t aa address data i/o previous data out valid data out valid t rc t oha t aa err previous err valid err valid t oha t aa notes 24. the device is continuously selected. oe = v il , ce = v il , bhe or ble or both = v il . 25. we is high for read cycle.
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 12 of 26 figure 10. read cycle no. 3 (oe controlled) [26, 27, 28] figure 11. write cycle no. 1 (ce controlled) [27, 29, 30] switching waveforms (continued) t rc t hzce t pd t ace t doe t lzoe t dbe t lzbe t lzce t pu high impedance data out valid high impedance address ce oe bhe/ ble data i/o v cc supply current t hzoe t hzbe i sb address ce we bhe/ ble data i/o oe t wc t sce t aw t sa t pwe t ha t bw t hd t hzoe t sd data in valid note 31 notes 26. we is high for read cycle. 27. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 28. address valid prior to or coincident with ce low transition. 29. the internal write time of the memory is defined by the overlap of we = v il , ce = v il and bhe or ble = v il . these signals must be low to initiate a write, and the high transition of any of these signals can terminate the operati on. the input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 30. data i/o is in high-impedance state if ce = v ih , or oe = v ih or bhe , and/or ble = v ih . 31. during this period, the i/os are in output state. do not apply input signals.
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 13 of 26 figure 12. write cycle no. 2 (we controlled, oe low) [32, 33, 34, 35] figure 13. write cycle no. 3 (we controlled) [32, 34, 35] 32. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 33. the minimum write pulse width for write cycle no. 2 (we controlled, oe low) should be sum of t hzwe and t sd . 34. the internal write time of the memory is defined by the overlap of we = v il , ce = v il and bhe or ble = v il . these signals must be low to initiate a write, and the high transition of any of these signals can terminate the operation. the input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 35. data i/o is in high-impedance state if ce = v ih , or oe = v ih or bhe , and/or ble = v ih . 36. during this period, the i/os are in output state. do not apply input signals. switching waveforms (continued) address ce data i/o t wc t sce t hd t sd t bw bhe/ ble t aw t ha t sa t pwe t lzw e t hzwe we data in valid note 36 address ce we bhe/ble data i/o oe t wc t sce t aw t sa t pw e t ha t bw t hd t hzoe t sd data in ? valid note 36
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 14 of 26 figure 14. write cycle no. 3 (ble or bhe controlled) [37, 38, 39] switching waveforms (continued) data in valid address ce we data i/o t wc t sce t aw t sa t bw t ha t hd t hzwe t sd bhe/ ble t pwe t lzwe note 40 notes 37. for all dual chip enable devices, ce is the logical combination of ce 1 and ce 2 . when ce 1 is low and ce 2 is high, ce is low; when ce 1 is high or ce 2 is low, ce is high. 38. the internal write time of the memo ry is defined by the overlap of we = v il , ce = v il and bhe or ble = v il . these signals must be low to initiate a write, and the high transition of any of these signals can terminate the operation. the input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 39. data i/o is in high-impedance state if ce = v ih , or oe = v ih , or bhe , and/or ble = v ih . 40. during this period, the i/os are in output state. do not apply input signals.
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 15 of 26 truth table ds ce oe we ble bhe i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power hhx [41] x [41] x [41] x [41] high-z high-z standby standby (i sb ) h l l h l l data out data out read all bits active (i cc ) h l l h l h data out high-z read lower bits only active (i cc ) h l l h h l high-z data out read upper bits only active (i cc ) h l x l l l data in data in write all bits active (i cc ) h l x l l h data in high-z write lower bits only active (i cc ) h l x l h l high-z data in write upper bits only active (i cc ) h l h h x x high-z high-z selected, outputs disabled active (i cc ) l [42] h x x x x high-z high-z deep sleep deep-sleep ultra low power (i ds ) l l x x x x ? ? invalid mode [43] ? h l x x h h high-z high-z selected, outputs disabled active (i cc ) err output ? cy7s1061ge output mode 0 read operation, no single-bit error in the stored data. 1 read operation, single-bit error detected and corrected. high-z device deselected or outputs disabled or write operation notes 41. the input voltage levels on these pins should be either at v ih or v il . 42. v il on ds must be < 0.2 v. 43. this mode does not guarantee data retention. power cycling needs to be performed for the device to return to normal operatio n.
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 16 of 26 ordering code definitions ordering information speed (ns) ordering code package diagram package type operating range 10 cy7s1061g30-10bvxi 51-85150 48-ball vfbg a (6 8 1.0 mm) (pb-free) industrial cy7s1061g30-10zxi 51-85183 48-pin tsop i (12 18.4 1.0 mm) (pb-free) cy7s1061g30-10zsxi 51-85160 54-pin tsop ii (22.4 11.84 1.0 mm) (pb-free) cy7s1061ge30-10zxi 51-85183 48-pin tsop i (12 18.4 1.0 mm) (pb-free), err output at pin 6 s cy 1 - 10 i 7 06 g 1 xx x temperature range: i = industrial pb-free package type: xx = bv or z or zs bv = 48-ball vfbga; z = 48-pin tsop i; zs = 54-pin tsop ii speed: 10 ns voltage range: 30 = 2.2 v to 3.6 v err output revision code ?g?: process technology ? 65 nm data width: 1 = 16-bits density: 06 = 16-mbit family code: 1 = fast asynchronous sram family s = deep-sleep feature marketing code: 7 = sram company id: cy = cypress 30 e
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 17 of 26 package diagrams figure 15. 48-ball vfbga (6 8 1.0 mm) bv48/bz48 package outline, 51-85150 51-85150 *h
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 18 of 26 figure 16. 48-pin tsop i (12 18.4 1.0 mm) z48a package outline, 51-85183 package diagrams (continued) 51-85183 *c
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 19 of 26 figure 17. 54-pin tsop ii (22.4 11. 84 1.0 mm) z54-ii p ackage outline, 51-85160 package diagrams (continued) 51-85160 *d
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 20 of 26 acronyms document conventions units of measure acronym description bhe byte high enable ble byte low enable ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable sram static random access memory ttl transistor-transistor logic vfbga very fine-pitch ball grid array we write enable symbol unit of measure c degree celsius mhz megahertz a microampere s microsecond ma milliampere mm millimeter ns nanosecond ohm % percent pf picofarad v volt w watt
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 21 of 26 errata this section describes the errata for the 16-mbit asynchronou s fast sram - cy7s1061g30 and cy7s1061ge30 - in 65-nm process technology. details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicabilit y. compare this document to the device?s datasheet for a complete functional description. if you have questions, contact your local cypress sales representative or raise a technical support case at www.cypress.com/go/support . part numbers affected fast sram [44] qualification status product status: all engineering samples ( note: reliability qualification is not complete. these samples are recommended to be used only for engineering builds and evaluation, and not for production builds). fast sram [44] errata summary this table defines the errata applicability to available 16-mbit devices. problem definition cy7s1061g30 and cy7s1061ge30 do not meet 10-ns speed in ac switching parameters as specified in ta b l e 1 . parameters affected ac switching parameters trigger condition functionality is not guaranteed when the device is operated at speed of 10 ns. scope of impact this issue may not pose problems for most end systems because they may incorporat e some margin to the dat asheet specifications. the deviation from the datasheet specified limit of 10 ns is 2 ns. workaround the ram controller timing needs additional margin to accommodate the slower speed. fix status the fix for the above issue is in progress. fixe d devices will be available from april 11, 2014. part number device characteristics cy7s1061g30 (all packages and options) 16-mbit fast sram cy7s1061ge30 (all packages and options) 16-mbit fast sram items part numbers silicon rev fix status fast sram [44] does not meet 10-ns speed-in ac switching parameters as specified in the datasheet specifications. cy7s1061g30 cy7s1061ge30 *a fixed devices to be available from april 11, 2014. note 44. this applies to all mpns mentioned in part numbers affected .
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 22 of 26 ac switching characteristics table 1. comparison of ac switching parameters for 10 ns and 12 ns part parameter description ? 10 ns ? 12 ns unit min max min max read cycle t rc read cycle time 10 ? 12 ? ns t aa address to data valid ? 10 ? 12 ns t oha data hold from address change 3 ? 3 ? ns t ace ce low to data valid ? 10 ? 12 ns t doe oe low to data valid ? 5 ? 7 ns t lzoe oe low to low-z 1 ? 1 ? ns t hzoe oe high to high-z ? 5 ? 7 ns t lzce ce low to low-z 3 ? 3 ? ns t hzce ce high to high-z ? 5 ? 7 ns t pu ce low to power-up 0 ? 0 ? ns t pd ce high to power-down ? 10 ? 12 ns t dbe byte enable to data valid ? 5 ? 7 ns t lzbe byte enable to low-z 1 ? 1 ? ns t hzbe byte disable to high-z ? 6 ? 7 ns write cycle t wc write cycle time 10 ? 12 ? ns t sce ce low to write end 7 ? 9 ? ns t aw address setup to write end 7 ? 9 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup to write start 0 ? 0 ? ns t pwe we pulse width 7 ? 9 ? ns t sd data setup to write end 5 ? 7 ? ns t hd data hold from write end 0 ? 0 ? ns t lzwe we high to low-z 3 ? 3 ? ns t hzwe we low to high-z ? 5 ? 7 ns t bw byte enable to end of write 7 ? 9 ? ns
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 23 of 26 document history page document title: cy7s1061g/cy7s1061ge, 16-mbit (1 m words 16 bit) static ram with deep-sleep feature and error correcting code (ecc) document number: 001-79707 rev. ecn no. orig. of change submission date description of change ** 3656657 tava 06/26/2012 new data sheet. *a 3776318 aju 10/30/2012 updated document title to ?16-mbit (1 m words 16 bit) static ram with deep-sleep feature?. updated features : highlighted typical and standby currents. changed operating voltage range from ?1.65 v to 5.5 v? to ?1.65 v to 2.2 v, 2.2 v to 3.6 v, 4.5 v to 5.5 v?. added 48-pin tsop i and 54-pin tsop ii pinouts, packages, and all related parameters. updated functional description (for better clarity). removed selection guide. updated logic block diagram - cy7s1061g (for better clarity). updated pin configurations : updated note 3 (for better clarity). updated product portfolio to list all product options. added typical values for i cc and i sb2 parameters. split v cc range in the second row from ?2.2 v?5.5 v? into two rows namely ?2.2 v?3.6 v? and ?4.5 v to 5.5 v?. updated note 1 for better clarity. updated operating range : changed v cc from ?1.65 v to 5.5 v? to ?1.65 v to 2.2 v, 2.2 v to 3.6 v, 4.5 v to 5.5 v?. changed latch up current limit from 200 to 140 ma (per jedec limits). updated dc electrical characteristics : changed maximum value of i cc parameter from 100 ma to 110 ma for the test condition f = 100 mhz. changed maximum value of i sb1 parameter from 30 ma to 40 ma. changed maximum value of i sb2 parameter from 25 ma to 30 ma. updated i sb2 and i ds test conditions to reflect correct cmos input levels. added footnotes 6 and 7. updated capacitance (changed c in and c out values from 8 pf to 10 pf). updated thermal resistance (changed thermal resistance values for 48-ball vfbga from 28.37, 5.79 to 31.50, 13.75 c/w). updated ac test loads and waveforms (added values for v high parameter in the table). updated data retention characteristics : changed maximum value of i ccdr parameter from 25 ma to 30 ma. added t ceds and t dsce parameters and their details. updated note 12 (for better clarity).
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 24 of 26 *a (cont.) 3776318 aju 10/30/2012 updated ac switching characteristics : removed t power parameter and associated note ?t power gives the minimum amount of time that the power supply is at typical v cc values until the first memory access? (spec captured in note 7). removed the note ?the minimum write cycle time for write cycle no. 2 (we controlled, oe low) is the sum of t hzwe and t sd .? and its references. updated note 13 to include difference in input levels for v cc operation of less than 3 v. updated note 22 for better clarity. updated switching waveforms : updated note 28 to correct typos. updated truth table : added notes 41 and 42. updated ordering information . updated package diagrams . *b 4003550 aju 05/17/2013 no technical updates. *c 4116197 memj 09/06/2013 updated document title to ?16-mbit (1 m words 16 bit) static ram with deep-sleep feature and error correcting code (ecc)?. updated features : changed i sb2 from 30 ma typical to 20ma typical. added ?embedded error correcting code (e cc) for single-bit error correction? updated v dr from 1.5 v to 1 v. updated functional description : added ecc description. updated logic block diagram - cy7s1061g : made ce 1 active low (replaced ce 1 with ce 1 ). updated data retention characteristics : changed minimum value of v dr from 1.5 v to 1.0 v. updated data retention waveform : changed v dr from 1.5 v to 1.0 v. updated ac switching characteristics : changed minimum value of t lzoe parameter from 1 ns to 0 ns for 10 ns speed bin. changed minimum value of t lzbe parameter from 1 ns to 0 ns for 10 ns speed bin. updated ordering information (updated part numbers). updated in new template. document history page (continued) document title: cy7s1061g/cy7s1061ge, 16-mbit (1 m words 16 bit) static ram with deep-sleep feature and error correcting code (ecc) document number: 001-79707 rev. ecn no. orig. of change submission date description of change
preliminary cy7s1061g, cy7s1061ge document number: 001-79707 rev. *g page 25 of 26 *d 4189510 memj 11/12/2013 updated pin configurations : added figure 4 . update dc electrical characteristics : added minimum value of i sb2 parameter. added note 8 and referred the same note in minimum value of i sb2 parameter. updated deep-sleep mode characteristics : referred note 15 in t ceds and t dsce parameters. updated ordering information (updated part numbers). *e 4272659 memj 02/06/2014 updated deep-sleep mode characteristics : renamed ?i dsdr ? as ?i ds ? in parameter column. updated ac switching characteristics : added note 19 and referred the same note in description of t lzoe , t hzoe , t lzce , t hzce , t lzbe , t hzbe , t lzwe , t hzwe parameters. *f 4292074 memj/vini 03/07/2014 updated features : added logic block diagram for cy7s1061ge specified i ds value as ?maximum? updated product portfolio added i ds typical of 8 a. update dc electrical characteristics : added column for typical values in dc electrical characteristics added i ds typical of 8 a updated note 10 to ?full device ac operation assumes a 100-s ramp time from 0 to v cc (min) and100-s wait time after v cc stabilization.? added note 13 in figure 6 . update ac switching characteristics added t power and associated note 17 added err timing information updated t sd from 5.5 ns to 5 ns. added note 23 and referr ed to write cycle timings updated switching waveforms changed title of figure 8 from ?read cycle no. 1? to ?read cycle no. 1 of cy7s1061g? added figure 13 (we controlled) added note 31 in figure 11 , note 36 in figure 12 , and note 40 in figure 14 to indicate i/os are in output state. added condition to place outputs in the disable state by making both bhe and ble high in truth table . added err output table added errata. *g 4330547 aju 04/02/2014 no content update. document history page (continued) document title: cy7s1061g/cy7s1061ge, 16-mbit (1 m words 16 bit) static ram with deep-sleep feature and error correcting code (ecc) document number: 001-79707 rev. ecn no. orig. of change submission date description of change
document number: 001-79707 rev. *g revised april 2, 2014 page 26 of 26 qdr rams and quad data rate rams comprise a new family of products developed by cypress, idt, nec, renesas, and samsung. all pr oducts and company names mentioned in this document may be the trademarks of their respective holders. preliminary cy7s1061g, cy7s1061ge ? cypress semiconductor corporation, 2012-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypre ss.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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